Memory devices are often packaged with more than one integrated circuit or “chip” in a single package. This multi-die (“stacked die”) packaging technique produces more memory locations in a single package than is available from a device having a single integrated circuit per package. Consequently, a higher memory location density per unit area in a finished electronic system can be achieved utilizing stacked die packages and techniques. The ability to implement stacked die memory solutions increases memory density in packaged memory devices, measured in memory bits per package. This is because the underlying chip memory density increase, measured in bits per chip, is dependent upon the semiconductor process technology improvements while the stacked die approach relies on existing packaging technology. The packaged memory density is essentially one generation ahead of the achievable chip memory density.
In a first conventional solution for memory depth expansion, as shown in FIG. 1, a plurality of memory devices are coupled together. Each memory die comprises chip enable (CE) inputs, both active high and active low. These chip enable inputs are configured, in one exemplary embodiment through bonding, so that only one die is selected at a given external address. For example, the chip enable inputs are treated as though they are a high order address input, and are not directly available outside the package as chip enable lines.
Disadvantages of the first conventional solution include the lack of a chip enable input to the package and that the address counter feature of some memory integrated circuits is not usable. An address counter feature is well known in single-die memory integrated circuits, e.g., the “CY7C0852V” random access memory (RAM) device commercially available from Cypress Semiconductor Corporation of San Jose, Calif.
For example, in the first conventional solution, the address range of the underlying memory chip is a fraction of that of the packaged multi-die implementation, e.g., one half for a package comprising two chips. One of the external address bus inputs to the packaged memory system is a chip enable (CE) input to the base memory die. The address counter of the underlying memory chip is not able to select between the multiple die in the package to determine which die is accessed by a given external package input address. The chip enable (CE) inputs, CE0b (chip enable 0 “bar”, active low) and CE1 (chip enable 1) are both used as external package address inputs to select between the multiple die packaged in the stacked die implementation.
In a second conventional solution for memory depth expansion, as shown in FIG. 2, a plurality of memory devices are coupled together. Each memory die comprises chip enable (CE) inputs, a bond option pin, and logic inside of the memory die to implement an exclusive-OR (XOR) combination of a control input (CESEL) with a chip enable signal. Disadvantages of the second conventional solution include that the address counter feature is not usable, as the address range of the underlying memory chip is one half of that of the packaged two-dice implementation. A further disadvantage of the second conventional solution is that one of the chip enable inputs, e.g., CE0b (chip enable 0 “bar”, active low), is used as an external package address input to select between the two dice packaged in the stacked die implementation and is therefore unavailable for use as a chip select input.
In a third conventional solution for memory width expansion, as shown in FIG. 3, a plurality of memory devices are coupled together. In this third solution the chip enable signals for each memory die are coupled together in a common manner such that all devices receive the same chip enable signals. By combining the data path from all individual chips together, the overall width of data storage is increased, e.g., doubled. A disadvantage of this solution is that both dice are maintained in an active, full function state, thus drawing more power than solutions in which only one die is active at a time. In addition, an internal data path multiplexer may be required so that the base die data path width is one half of the data path width of the external data path. Such a data path multiplexer generally deleteriously slows down memory accesses.
It would be desirable to have a solution that overcomes the disadvantages of the conventional solutions. It is also desirable to accomplish the depth expansion while keeping the full feature set of the underlying memory integrated circuit.